Design and Performance Evaluation of a Fault - Tolerant Input - Buffered ATM Switch based on Multistage Interconnection Networks


The KIPS Transactions:PartC, Vol. 8, No. 3, pp. 319-326, Jun. 2001
10.3745/KIPSTC.2001.8.3.319,   PDF Download:

Abstract

In this paper, we present an input-buffered ATM switch architecture based on multistage interconnection networks. The proposed scheme can solve the problem which limits the maximum throughput to about 58.6% under uniform traffic because of the HOL (head-of-line) blocking, and then proposes the scheme to give multiple paths in order to expand fault tolerant function by using Buddy and Constrained connection Mapping properties of the Baseline network. The result of performance evaluation by simulation shows that the proposed scheme has a good throughput and cell loss rate. In addition, the level of throughput is maintained with acceptable cell delay even though the number of faulty components increases.


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Cite this article
[IEEE Style]
W. C. Synn and Y. E. Son, "Design and Performance Evaluation of a Fault - Tolerant Input - Buffered ATM Switch based on Multistage Interconnection Networks," The KIPS Transactions:PartC, vol. 8, no. 3, pp. 319-326, 2001. DOI: 10.3745/KIPSTC.2001.8.3.319.

[ACM Style]
Won Chul Synn and Yoo Ek Son. 2001. Design and Performance Evaluation of a Fault - Tolerant Input - Buffered ATM Switch based on Multistage Interconnection Networks. The KIPS Transactions:PartC, 8, 3, (2001), 319-326. DOI: 10.3745/KIPSTC.2001.8.3.319.