Design and FPGA Implementation of a High - Speed RSA Algorithm for Digital Signature


The KIPS Transactions:PartC, Vol. 8, No. 1, pp. 32-40, Feb. 2001
10.3745/KIPSTC.2001.8.1.32,   PDF Download:

Abstract

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of SynopsysTM tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.


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Cite this article
[IEEE Style]
M. S. Kang and D. W. Kim, "Design and FPGA Implementation of a High - Speed RSA Algorithm for Digital Signature," The KIPS Transactions:PartC, vol. 8, no. 1, pp. 32-40, 2001. DOI: 10.3745/KIPSTC.2001.8.1.32.

[ACM Style]
Min Sup Kang and Dong Wook Kim. 2001. Design and FPGA Implementation of a High - Speed RSA Algorithm for Digital Signature. The KIPS Transactions:PartC, 8, 1, (2001), 32-40. DOI: 10.3745/KIPSTC.2001.8.1.32.