Hong Jun Choi , Dong Oh Son , Jong Myon Kim , Cheol Hong Kim

The KIPS Transactions:PartA, Vol. 17, No. 6, pp. 265-274, Dec. 2010
10.3745/KIPSTA.2010.17.6.265,   PDF Download:

Abstract

As the process technology scales down and integration densities continue to increase. interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicol1 vias). Compared to 2D mi-core architecture, 3D multi-core architecture reduces wire length significantly. leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper. we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results. the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

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