TY  - JOUR
T1  - Design and Evaluation of 32-Bit RISC-V Processor Using FPGA
AU  - Jang, Sungyeong 
AU  - Park, Sangwoo 
AU  - Kwon, Guyun 
AU  - Suh, Taeweon 
JO  - KIPS Transactions on Computer and Communication Systems
PY  - 2022
DA  - 2022/1/30
DO  - https://doi.org/10.3745/KTCCS.2022.11.1.1
KW  - RISC-V
KW  - FPGA
KW  - Processor
AB  - RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the
purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded
systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK
instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W
on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to
compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark
benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for
future extension.