Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory


KIPS Transactions on Computer and Communication Systems, Vol. 5, No. 1, pp. 1-6, Jan. 2016
10.3745/KTCCS.2016.5.1.1,   PDF Download:

Abstract

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
J. W. Seo and M. Choi, "Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory," KIPS Transactions on Computer and Communication Systems, vol. 5, no. 1, pp. 1-6, 2016. DOI: 10.3745/KTCCS.2016.5.1.1.

[ACM Style]
Ju Wan Seo and Min Choi. 2016. Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory. KIPS Transactions on Computer and Communication Systems, 5, 1, (2016), 1-6. DOI: 10.3745/KTCCS.2016.5.1.1.