Eum Si Woo, Jang Kyung Bae, Song Gyeong Ju, Lee Min Woo, Seo Hwa Jeong

KIPS Transactions on Computer and Communication Systems, Vol. 11, No. 6, pp. 167-174, Jun. 2022
https://doi.org/10.3745/KTCCS.2022.11.6.167,   PDF Download:
Keywords: PIPO, RISC-V, Lightweight Block cipher, Optimization Implementation
Abstract

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

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