Architecture Design of Turbo Codec using on-the-fly interleaving


The KIPS Transactions:PartC, Vol. 10, No. 2, pp. 233-240, Apr. 2003
10.3745/KIPSTC.2003.10.2.233,   PDF Download:

Abstract

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interation numbers, interleaver block sizes and code rates.


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Cite this article
[IEEE Style]
S. G. Lee, N. U. Song, Y. C. Kay, "Architecture Design of Turbo Codec using on-the-fly interleaving," The KIPS Transactions:PartC, vol. 10, no. 2, pp. 233-240, 2003. DOI: 10.3745/KIPSTC.2003.10.2.233.

[ACM Style]
Sung Gyu Lee, Nag Un Song, and Yong Chul Kay. 2003. Architecture Design of Turbo Codec using on-the-fly interleaving. The KIPS Transactions:PartC, 10, 2, (2003), 233-240. DOI: 10.3745/KIPSTC.2003.10.2.233.