Digital Library


Search: "[ keyword: Verilog HDL ]" (2)
    Design of Iterative Divider in GF(2(163)) Based on Improved Binary Extended GCD Algorithm
    Min Sup Kang , Byong Chan Jeon KIPS Transactions on Computer and Communication Systems, Vol. 17, No. 2, pp. 145-152, Feb. 2010
    10.3745/KIPSTC.2010.17.2.145

    Design of Optimized ARIA Crypto-Processor Using Composite Field S-Box
    Kang Min Sup KIPS Transactions on Computer and Communication Systems, Vol. 8, No. 11, pp. 271-276, Nov. 2019
    https://doi.org/10.3745/KTCCS.2019.8.11.271
    Keywords: ARIA Crypto-Processor, Composite Field S-Box, Key scheduling, Verilog HDL