A New TRF Delay Model for the Efficient Hazard Analysis in a 5-valued Logic Simulation


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 4, No. 4, pp. 1004-1012, Apr. 1997
10.3745/KIPSTE.1997.4.4.1004,   PDF Download:

Abstract

This paper proposes a new TRF (Transition Rise/Fall) delay model for the effiecient hazard analysis in a 5-valued logic simulation environment. For the hazard for a given logic circuit, the timing analysis is first performed by means of a 5-valued logic simulator which uses the TRF delay model which incorporates the response delay for a response state with the transition delay for a transition state of an element, and then hazards are detected through investigating timing relations. Simulation examples and experimental results are also given to demonstrate the practicability of the proposed methos.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
K. M. Sup, "A New TRF Delay Model for the Efficient Hazard Analysis in a 5-valued Logic Simulation," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 4, pp. 1004-1012, 1997. DOI: 10.3745/KIPSTE.1997.4.4.1004.

[ACM Style]
Kang Min Sup. 1997. A New TRF Delay Model for the Efficient Hazard Analysis in a 5-valued Logic Simulation. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 4, (1997), 1004-1012. DOI: 10.3745/KIPSTE.1997.4.4.1004.