An Effective Parallel and Pipelined Algorithm with Minimum Delayed Time in VLIW System


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 2, No. 4, pp. 466-476, Jul. 1995
10.3745/KIPSTE.1995.2.4.466,   PDF Download:

Abstract

This paper describes pipelining algorithm issues for a VLIW(Very Long Instruction Word) System and the effective pipelined processing method by occurrence in pipelined mamegement of processor minimized to timing delay. The proposed algorithm is executed in pipeline and parallel processings, and by combining basic operations variable instruction set can be designed for various applications. In this paper, we prove and analyze the efficiency of the proposed pipeline algorithm and compare with other processor pipeline algorithm in terms of time minimizing.


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Cite this article
[IEEE Style]
S. J. Won, S. J. Hee, R. C. Yeol, J. M. Seog, "An Effective Parallel and Pipelined Algorithm with Minimum Delayed Time in VLIW System," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 4, pp. 466-476, 1995. DOI: 10.3745/KIPSTE.1995.2.4.466.

[ACM Style]
Suh Jang Won, Song Jin Hee, Ryou Chun Yeol, and Jun Moon Seog. 1995. An Effective Parallel and Pipelined Algorithm with Minimum Delayed Time in VLIW System. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 4, (1995), 466-476. DOI: 10.3745/KIPSTE.1995.2.4.466.