Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy


KIPS Transactions on Computer and Communication Systems, Vol. 5, No. 12, pp. 439-446, Dec. 2016
10.3745/KTCCS.2016.5.12.439, Full Text:
Keywords: Verification, Event-Driven Logic Simulation, Parallel Logic Simulation
Abstract

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction- based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.


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Cite this article
[IEEE Style]
S. Yang, "Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy," KIPS Transactions on Computer and Communication Systems, vol. 5, no. 12, pp. 439-446, 2016. DOI: 10.3745/KTCCS.2016.5.12.439.

[ACM Style]
Seiyang Yang. 2016. Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy. KIPS Transactions on Computer and Communication Systems, 5, 12, (2016), 439-446. DOI: 10.3745/KTCCS.2016.5.12.439.