The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System


KIPS Transactions on Computer and Communication Systems, Vol. 3, No. 12, pp. 443-448, Dec. 2014
10.3745/KTCCS.2014.3.12.443, Full Text:

Abstract

This paper is a study related to fault tolerant design based on PSTR using virtualization techniques. If the fault tolerant PSTR based on virtualization techniques is implemented the communication performance between primary and shadow will improves and monitoring function is easy to available about activities of primary and shadow. The legacy PSTR model is implemented in its hardware. The primary play a main role and shadow play a switched action when the errors occurrs in the primary. The switched action of shadow make it possible to restart the primary function newly. This paper implements fault tolerant primary-shadow model using virtualization techniques on the embedded environment.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
J. H. Yoo and K. J. An, "The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System," KIPS Transactions on Computer and Communication Systems, vol. 3, no. 12, pp. 443-448, 2014. DOI: 10.3745/KTCCS.2014.3.12.443.

[ACM Style]
Jin Ho Yoo and Kyu Jong An. 2014. The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System. KIPS Transactions on Computer and Communication Systems, 3, 12, (2014), 443-448. DOI: 10.3745/KTCCS.2014.3.12.443.