Gate Sizing Of Multiple-paths Circuit

KIPS Transactions on Computer and Communication Systems, Vol. 2, No. 3, pp. 103-110, Mar. 2013
10.3745/KTCCS.2013.2.3.103,   PDF Download:


Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.

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Cite this article
[IEEE Style]
J. K. Chang and S. H. Lee, "Gate Sizing Of Multiple-paths Circuit," KIPS Transactions on Computer and Communication Systems, vol. 2, no. 3, pp. 103-110, 2013. DOI: 10.3745/KTCCS.2013.2.3.103.

[ACM Style]
Jong Kwon Chang and Seung Ho Lee. 2013. Gate Sizing Of Multiple-paths Circuit. KIPS Transactions on Computer and Communication Systems, 2, 3, (2013), 103-110. DOI: 10.3745/KTCCS.2013.2.3.103.