Performance Analysis of Synchronization Clock with Various Clock States Using Measured Clock Noises in NG-SDH Networks


The KIPS Transactions:PartC, Vol. 16, No. 5, pp. 637-644, Oct. 2009
10.3745/KIPSTC.2009.16.5.637,   PDF Download:

Abstract

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.


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Cite this article
[IEEE Style]
C. K. Lee, "Performance Analysis of Synchronization Clock with Various Clock States Using Measured Clock Noises in NG-SDH Networks," The KIPS Transactions:PartC, vol. 16, no. 5, pp. 637-644, 2009. DOI: 10.3745/KIPSTC.2009.16.5.637.

[ACM Style]
Chang KI Lee. 2009. Performance Analysis of Synchronization Clock with Various Clock States Using Measured Clock Noises in NG-SDH Networks. The KIPS Transactions:PartC, 16, 5, (2009), 637-644. DOI: 10.3745/KIPSTC.2009.16.5.637.