Simulation Method based on Design Checkpoint for Efficient Debugging


The KIPS Transactions:PartA, Vol. 19, No. 3, pp. 113-120, Jun. 2012
10.3745/KIPSTA.2012.19.3.113,   PDF Download:

Abstract

The visibility for signals in designs is required for their analysis and debug during the verification process. It could be achieved through the signal dumping for designs during the execution of HDL simulation. However, such signal dumping, in general, degrades the speed of simulation significantly, or can result in the number of simulation runs. In this paper, we have proposed an efficient and fast simulation method for dumping based on the design checkpoint, and shown its effectiveness by applying it to industrial SOC designs.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
K. H. Shim, N. D. Kim, I. H. Park, B. Eon, S. Y. Yang, "Simulation Method based on Design Checkpoint for Efficient Debugging," The KIPS Transactions:PartA, vol. 19, no. 3, pp. 113-120, 2012. DOI: 10.3745/KIPSTA.2012.19.3.113.

[ACM Style]
Kyu Ho Shim, Nam Do Kim, In Hag Park, Byeong Eon, and Sei Yang Yang. 2012. Simulation Method based on Design Checkpoint for Efficient Debugging. The KIPS Transactions:PartA, 19, 3, (2012), 113-120. DOI: 10.3745/KIPSTA.2012.19.3.113.