Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor


The KIPS Transactions:PartA, Vol. 18, No. 6, pp. 265-270, Dec. 2011
10.3745/KIPSTA.2011.18.6.265,   PDF Download:

Abstract

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
H. K. Lee, S. W. Kim, Y. S. Han, "Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor," The KIPS Transactions:PartA, vol. 18, no. 6, pp. 265-270, 2011. DOI: 10.3745/KIPSTA.2011.18.6.265.

[ACM Style]
Ho Kyoon Lee, Seon Wook Kim, and Young Sun Han. 2011. Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor. The KIPS Transactions:PartA, 18, 6, (2011), 265-270. DOI: 10.3745/KIPSTA.2011.18.6.265.