Low-Power Data Cache Architecture and Microarchitecture-Level Management Policy for Multimedia Application


The KIPS Transactions:PartA, Vol. 13, No. 3, pp. 191-198, Jun. 2006
10.3745/KIPSTA.2006.13.3.191,   PDF Download:

Abstract

Today’s portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
H. M. Yang, C. G. Kim, G. H. Park, S. D. Kim, "Low-Power Data Cache Architecture and Microarchitecture-Level Management Policy for Multimedia Application," The KIPS Transactions:PartA, vol. 13, no. 3, pp. 191-198, 2006. DOI: 10.3745/KIPSTA.2006.13.3.191.

[ACM Style]
Hoon Mo Yang, Cheong Gil Kim, Gi Ho Park, and Shin Dug Kim. 2006. Low-Power Data Cache Architecture and Microarchitecture-Level Management Policy for Multimedia Application. The KIPS Transactions:PartA, 13, 3, (2006), 191-198. DOI: 10.3745/KIPSTA.2006.13.3.191.