Hardware/Software Partitioning Methodology for Reconfigurable System


KIPS Transactions on Computer and Communication Systems, Vol. 11, No. 5, pp. 303-312, May. 2004
10.3745/KIPSTA.2004.11.5.303, Full Text:

Abstract

In this paper, we propose a methodology solving the problem of the hardware-software partitioning in reconfigurable systems using a Y-chart design space exploration and implement a simulator according to the methodology. The methodology generates a mapping set between tasks and hardware elements using the hardware element model and the application model. We evaluate the throughput by simulating cases in each mapping set. With the throughput evaluation result, we can select the mapping case with the highest throughput. We also propose an heuristic improving the simulation time by reducing the mapping set on the basis of the relationship between workload and parallelism. Simulation results show that we can reduce the size of mapping set which poses difficulties on hardware-software partitioning by up to 80%.


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Cite this article
[IEEE Style]
J. Y. Kim, S. Y. Ahn and J. A. Lee, "Hardware/Software Partitioning Methodology for Reconfigurable System," KIPS Journal A (2001 ~ 2012) , vol. 11, no. 5, pp. 303-312, 2004. DOI: 10.3745/KIPSTA.2004.11.5.303.

[ACM Style]
Jun Yong Kim, Seong Yong Ahn, and Jeong A Lee. 2004. Hardware/Software Partitioning Methodology for Reconfigurable System. KIPS Journal A (2001 ~ 2012) , 11, 5, (2004), 303-312. DOI: 10.3745/KIPSTA.2004.11.5.303.