Computer Graphics & Synthesizable Synchronous VHDL Code Generator Design and Implemetation from SpecCharts


KIPS Transactions on Computer and Communication Systems, Vol. 7, No. 11, pp. 3566-3575, Nov. 2000
10.3745/KIPSTE.2000.7.11.3566, Full Text:

Abstract

We are using a methodology of virtual prototype(VP) which can reduce costs and developement time to the market. VP is composed of S/W component, H/W component, and interface component which links H/W to S/W. There are many methods of realizing H/W components, but we adopt a method which translates from system specification into hardware description in VHDL. In this paper, we present design and implementation of code generator from SpecCharts as system specification language to a VHDL code which can be synthesized and verified. The verification becomes feasible when the hardware satisfies synchronous semantics, which we call, Synchronous VHDL.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from September 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.


Cite this article
[IEEE Style]
S. J. Yun, J. Y. Choi, S. Y. Han, J. A. Lee, W. Y. Yoo, J. I. Choi and J. W. Lee, "Computer Graphics & Synthesizable Synchronous VHDL Code Generator Design and Implemetation from SpecCharts," KIPS Journal (1994 ~ 2000), vol. 7, no. 11, pp. 3566-3575, 2000. DOI: 10.3745/KIPSTE.2000.7.11.3566.

[ACM Style]
Seong Jo Yun, Jin Young Choi, Sang Yong Han, Jeong A Lee, Won Young Yoo, Jeong Il Choi, and Joon Whoan Lee. 2000. Computer Graphics & Synthesizable Synchronous VHDL Code Generator Design and Implemetation from SpecCharts. KIPS Journal (1994 ~ 2000), 7, 11, (2000), 3566-3575. DOI: 10.3745/KIPSTE.2000.7.11.3566.