Distrbuted Processing and Minimum Design of Fault-Tolerant Arrangement Graph for Distributed & Parallel System


The Transactions of the Korea Information Processing Society (1994 ~ 2000), Vol. 5, No. 12, pp. 3088-3098, Dec. 1998
10.3745/KIPSTE.1998.5.12.3088,   PDF Download:

Abstract

The arrangement graph, which is a viable interconnection scheme for parallel and distributed systems, has been proposed as an attractive alternative to th n-cube. However. A fault -tolerant design model which is well suitable for the arrangement graph doesn't has been proposed until recently, but fault-tolerant design models for many schemes have been proposed in a large number of paper. So, our paper presents a new fault-tolerant design technique suited for the arrangement graph. To maintains the previous structures when it occurs a fault in the current processing, the scheme properly substitutes a fault-component into the existing structures by adding a spare component. The first of all, it converts arrangement graph into a circulant graph using the hamiltonian property and then uses automorphism of circulant graph to tolerate faults. Also, We optimize the cost of rate fault-tolerant architectures by adding exactly k spare processors(while tolerating up to k processor) and minimizing the maximum number of links per processor. Specially, we proposes a new technique to minimize the maximum number of links.


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Cite this article
[IEEE Style]
J. M. Seog and L. M. Gu, "Distrbuted Processing and Minimum Design of Fault-Tolerant Arrangement Graph for Distributed & Parallel System," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 12, pp. 3088-3098, 1998. DOI: 10.3745/KIPSTE.1998.5.12.3088.

[ACM Style]
Jun Moon Seog and Lee Moon Gu. 1998. Distrbuted Processing and Minimum Design of Fault-Tolerant Arrangement Graph for Distributed & Parallel System. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 12, (1998), 3088-3098. DOI: 10.3745/KIPSTE.1998.5.12.3088.